View HY62SF16804A-I_682997.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HY62SF16804A Series
512Kx16bit full CMOS SRAM
Document Title
512K x16 bit 1.8V Super Low Power Full CMOS slow SRAM
Revision History
Revision No 04 History Initial Revision History Insert Revised - Reliability Spec Deleted Change AC Characteristics - tCLZ : 10/10/20 ---> 10/10/10 - tBLZ : 5/5/5 ---> 10/10/10 Part Number is changed - HY62QF16803A --> HY62QF16804A Marking Instruction is inserted Test Condition Changed - ILO / ISB / ISB1 / VDR / ICCDR Marking Istruction Inserted Change Logo - Hyundai a Hynix AC Parameter is changed - tCHZ : 30ns --> 20ns - tBHZ : 30ns --> 20ns - tOHZ : 30ns --> 20ns Change DC Parameter - Icc1(1us) : 5mA a 4mA Change Data Retention - IccDR(LL) : 25uA a 15uA Change AC Parameter - tOE : 40ns a 35ns@70ns Draft Date Jul.02.2000 Remark Preliminary
05
Oct.23.2000
Preliminary
06
Nov.13.2000
Preliminary
07 08
Dec.5.2000 Dec.16.2000
Preliminary Preliminary
09
Apr.28.2001
10
Jul.18.2001
11
Jan.28.2002
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev.11 /Jan. 2002 Hynix Semiconductor
HY62SF16804A
DESCRIPTION
The HY62SF16804A is a high speed, super low power and 8Mbit full CMOS SRAM organized as 524,288 words by 16bits. The HY62SF16804A uses high performance full CMOS process technology and is designed for high speed and low power circuit technology. It is particularly wellsuited for the high density low power system application. This device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 1.2V. Product Voltage Speed No. (V) (ns) HY62SF16804A-C 1.7~2.3 70/85/100 HY62SF16804A-I 1.7~2.3 70/85/100 Note 1. C : Commercial, I : Industrial 2. Current value is max.
FEATURES
* Fully static operation and Tri-state output * TTL compatible inputs and outputs * Battery backup(LL/SL-part) - 1.2V(min) data retention * Standard pin configuration - 48-uBGA
Operation Current/Icc(mA) 3 3
Standby Current(uA) LL SL 25 8 25 8
Temperature (C) 0~70 -40~85
PIN CONNECTION ( Top View )
/LB /OE A0 A1 A4 A6 A2 NC
A1,A2 A4,A6~A7 A9 A12 A15~A18 A8
BLOCK DIAGRAM
ADD INPUT BUFFER ROW DECODER SENSE AMP I/O1
IO9 /UB A3 IO10 IO11 A5
/CS IO1 IO2 IO3 IO4 Vcc
COLUMN DECODER
I/O8 DATA I/O BUFFER
ADD INPUT BUFFER
PRE DECODER
Vss IO12 A17 A7
A10 A13 A14 A0 A3 A5
Vcc IO13 Vss A16 IO5 Vss IO15 IO14 A14 A15 IO6 IO7 IO16 NC A18 A8 A12 A13 /WE IO8 A9 A10 A11 NC
MEMORY ARRAY 512K x 16
WRITE DRIVER
I/O9
BLOCK DECODER
ADD INPUT BUFFER
I/O16
A11 /CS /OE /LB /UB /WE
PIN DESCRIPTION
Pin Name /CS /WE /OE /LB /UB Pin Function Chip Select Write Enable Output Enable Lower Byte Control(I/O1~I/O8) Upper Byte Control(I/O9~I/O16) Pin Name I/O1~I/O16 A0~A18 Vcc Vss NC Pin Function Data Inputs / Outputs Address Inputs Power(1.7V~2.3V) Ground No Connection
Rev.11 /Jan. 2002
2
HY62SF16804A
ORDERING INFORMATION
Part No. Speed HY62SF16804A-DMC 70/85/100 HY62SF16804A-SMC 70/85/100 HY62SF16804A-DMI 70/85/100 HY62SF16804A-SMI 70/85/100 Note 1. C : Commercial, I : Industrial Power LL-part SL-part LL-part SL-part Package uBGA uBGA uBGA uBGA Temp. C C I I
ABSOLUTE MAXIMUM RATINGS (1)
Symbol VIN, VOUT Vcc TA Parameter Input/Output Voltage Power Supply Operating Temperature Rating -0.2 to 3.6 -0.2 to 4.6 0 to 70 -40 to 85 -55 to 150 1.0 260 * 10 Unit V V C C C W C * sec Remark
HY62SF16804A-C HY62SF16804A-I
TSTG Storage Temperature PD Power Dissipation TSOLDER Ball Soldering Temperature & Time Note 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect reliability.
TRUTH TABLE
/CS H X L L L /WE X X H H H /OE X X H H L /LB X H L X L H L L H L /UB X H X L H L L H L L Mode Deselected Deselected Output Disabled Output Disabled Read I/O1~I/O8 High-Z High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN I/O I/O9~I/O16 High-Z High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN Power Standby Standby Active Active Active
L
L
X
Write
Active
Note: 1. H=VIH, L=VIL, X=don't care(VIH or VIL) 2. UB, LB(Upper, Lower Byte enable) These active LOW inputs allow individual bytes to be written or read. When LB is LOW, data is written or read to the lower byte, I/O1 -I/O8. When UB is LOW, data is written or read to the upper byte, I/O9 -I/O16.
Rev.11 /Jan. 2002
2
HY62SF16804A
RECOMMENDED DC OPERATING CONDITION
Symbol Vcc Vss VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 1.7 0 1.4 -0.3(1) Typ. 1.8 0 Max. 2.3 0 Vcc+0.3 0.4 Unit V V V V
Note : 1. VIL = -1.5V for pulse width less than 30ns
DC ELECTRICAL CHARACTERISTICS
Vcc = 1.7V~2.3V, TA = 0C to 70C / -40C to 85C Sym Parameter Test Condition ILI Input Leakage Current Vss < VIN < Vcc Vss < VOUT < Vcc, /CS = VIH or ILO Output Leakage Current /OE = VIH or /WE = VIL, /UB = /LB = VIH Operating Power Supply Icc /CS = VIL, VIN = VIH or VIL, II/O = 0mA Current Cycle Time=Min,100% duty, II/O = 0mA, /CS = VIL,VIN = VIH or VIL Average Operating Icc1 Current Cycle time = 1us, 100% duty, II/O = 0mA, /CS < 0.2V, VIN<0.2V /CS = VIH or /UB=/LB= VIH, TTL Standby Current ISB (TTL Input) VIN = VIH or VIL /CS > Vcc - 0.2V or SL Standby Current /UB=/LB > Vcc-0.2V, ISB1 (CMOS Input) VIN > Vcc-0.2V or LL VIN < Vss+0.2V VOL Output Low Voltage IOL = 0.1mA VOH Output High Voltage IOH = -0.1mA Note : 1. Typical values are at Vcc = 1.8V, TA = 25C 2. Typical values are sampled and not 100% tested Min. -1 -1 1.4 1 Typ. Max. 1 1 3 25 4 0.3 8 25 0.4 Unit uA uA mA mA mA mA uA uA V V
CAPACITANCE
(Temp = 25C, f = 1.0MHz) Symbol Parameter CIN Input Capacitance(Add, /CS, /WE, /OE) COUT Output Capacitance(I/O) Condition VIN = 0V VI/O = 0V Max. 8 10 Unit pF pF
Note : These parameters are sampled and not 100% tested
Rev.11 /Jan. 2002
3
HY62SF16804A
AC CHARATERISTICS
Vcc = 1.7V~2.3V, TA = 0C to 70C / -40C to 85C # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Symbol Parameter -70 Min. Max. 70 10 5 10 0 0 0 10 70 60 60 60 0 50 0 0 30 0 5 70 70 35 70 20 20 20 25 -85 Min. Max. 85 10 5 10 0 0 0 10 85 70 70 70 0 55 0 0 35 0 5 85 85 45 85 30 30 30 30 -10 Min Max. 100 10 5 10 0 0 0 15 100 80 80 80 0 75 0 0 45 0 10 100 100 50 100 30 30 30 35 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
READ CYCLE tRC Read Cycle Time tAA Address Access Time tACS Chip Select Access Time tOE Output Enable to Output Valid tBA /LB, /UB Access Time tCLZ Chip Select to Output in Low Z tOLZ Output Enable to Output in Low Z tBLZ /LB, /UB Enable to Output in Low Z tCHZ Chip Deselection to Output in High Z tOHZ Out Disable to Output in High Z tBHZ /LB, /UB Disable to Output in High Z tOH Output Hold from Address Change WRITE CYCLE tWC Write Cycle Time tCW Chip Selection to End of Write tAW Address Valid to End of Write tBW /LB, /UB Valid to End of Write tAS Address Set-up Time tWP Write Pulse Width tWR Write Recovery Time tWHZ Write to Output in High Z tDW Data to Write Time Overlap tDH Data Hold from Write Time tOW Output Active from End of Write
AC TEST CONDITIONS
TA = 0C to 70C / -40C to 85C, unless otherwise specified PARAMETER Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Level tCLZ,tOLZ,tBLZ,tCHZ,tOHZ,tBHZ,tWHZ,tOW Output Load Other Value 0.4V to 1.6V 5ns 0.9V CL = 5pF + 1TTL Load CL = 30pF + 1TTL Load
AC TEST LOADS
VTM = 1.8V
4091 Ohm D
OUT
CL(1)
3273 Ohm
Note 1. Including jig and scope capacitance
Rev.11 /Jan. 2002
4
HY62SF16804A
TIMING DIAGRAM
READ CYCLE 1(Note 1,4)
tRC ADDR tAA tACS /CS tCHZ(3) tBA /UB ,/ LB tOE tOLZ(3) tBLZ(3) tCLZ(3) Data Valid tBHZ(3) tOH
/OE
tOHZ(3)
Data Out
High-Z
READ CYCLE 2(Note 1,2,4)
tRC ADDR tAA tOH Data Out Previous Data Data Valid tOH
READ CYCLE 3(Note 1,2,4)
/CS /UB, /LB
tACS tCLZ(3) Data Out Data Valid tCHZ(3)
Notes: 1. A read occurs during the overlap of a low /OE, a high /WE, a low /CS1 and low /UB and /or /LB 2. /OE = VIL 3. Transition is measured + 200mV from steady state voltage. This parameter is sampled and not 100% tested. 4. /CS in high for the standby, low for active /UB and /LB in high for the standby, low for active
Rev.11 /Jan. 2002
5
HY62SF16804A
WRITE CYCLE 1 (1,4,8) (/WE Controlled)
tWC ADDR tWR(2) tCW /CS tAW tBW /UB,/LB tWP /WE tAS Data In High-Z tWHZ(3,7) Data Out tDW Data Valid tOW (5) (6) tDH
WRITE CYCLE 2 (Note 1,4,8) (/CS Controlled)
tWC ADDR tAS /CS tAW tBW /UB,/LB tWP /WE tDW Data In High-Z Data Valid tDH tCW tWR(2)
Data Out
High-Z
Rev.11 /Jan. 2002
6
HY62SF16804A
Notes: 1. A write occurs during the overlap of a low / WE, a low /CS1 and low /UB and /or /LB 2. tWR is measured from the earlier of /CS, /LB, /UB, or /WE going high to the end of write cycle. 3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be applied. 4. If the /CS, /LB and /UB low transition occur simultaneously with the /WE low transition or after the /WE transition, outputs remain in a high impedance state. 5. Q(data out) is the same phase with the write data of this write cycle. 6. Q(data out) is the read data of the next address. 7. Transition is measured +200mV from steady state. This parameter is sampled and not 100% tested. 8. /CS in high for the standby, low for active /UB and /LB in high for the standby, low for active
DATA RETENTION ELECTRIC CHARACTERISTIC
TA = 0C to 70C / -40C to 85C Symbol Parameter VDR Vcc for Data Retention Test Condition /CS > Vcc - 0.2V or /UB=/LB > Vcc-0.2V, VIN > Vcc-0.2V or VIN < Vss+0.2V Vcc=1.5V, /CS > Vcc - 0.2V or /UB=/LB > Vcc-0.2V, VIN > Vcc-0.2V or VIN < Vss+0.2V Min 1.2 LL SL 0 tRC(2) Typ Max 2.3 15 8 Unit V uA uA ns ns
ICCDR
Data Retention Current Chip Deselect to Data Retention Time Operating Recovery Time
tCDR tR
See Data Retention Timing Diagram
Notes: 1. Typical values are under the condition of TA = 25C . 2. tRC is read cycle time.
DATA RETENTION TIMING DIAGRAM
VCC 1.7V tCDR DATA RETENTION MODE tR
VIH VDR /CS or /UB & /LB Vss /CS>Vcc-0.2V or /UB=/LB > Vcc-0.2V
Rev.11 /Jan. 2002
7
HY62SF16804A
PACKAGE INFORMATION
48ball Micro Ball Grid Array Package(M)
BOTTOM VIEW
B A A1 CORNER INDEX AREA 6 A A B C D C E F G H C1/2 3.0 X 5.0 MIN FLAT AREA 5 4 3 2 1
TOP VIEW
C1
B1/2
B1
SIDE VIEW
5
C
E1 E2 E SEATING PLANE A 4
r
3 D(DIAMETER)
Symbol A B B1 C C1 D E E1 E2 r
Min. 0.3 0.85 0.6 0.2 -
Typ. 0.75 3.75 7.4 5.25 8.5 0.35 0.9 0.65 0.25 -
Max. 0.4 0.95 0.7 0.3 0.08
Note 1. DIMENSIONING AND TOLERANCING PER ASME Y14. 5M-1994. 2. ALL DIMENSIONS ARE MILLIMETERS. 3. DIMENSION " D" IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 4. PRIMARY DATUM C(SEATING PLANE) IS DEFINED BY THE CROWN OF THE SOLDER BALLS. 5. THIS IS A CONTROLLING DIMENSION.
Rev.11 /Jan. 2002
8
HY62SF16804A
MARKING INSTRUCTION
Package
H Y
Marking Example
S F 6 8 0 4 A
uBGA
c
s
s
t
y
w
w
p
x
x
x
x
x
K
O
R
Index
* HYSF6804A *c : Part Name : Power Consumption -D -S : Speed - 55 - 70 - 85 *t : Temperature -C -I : 55ns : 70ns : 85ns : Commercial ( -0 ~ 70 C ) : Industrial ( -40 ~ 85 C )
: Low Low Power : Super Low Power
* ss
*y * ww *p * xxxxx * KOR Note - Capital Letter - Small Letter
: Year (ex : 0 = year 2000, 1= year 2001) : Work Week ( ex : 12 = work week 12 ) : Process Code : Lot No. : Origin Country
: Fixed Item : Non-fixed Item
Rev.11 /Jan. 2002
9

▲Up To Search▲

Price & Availability of HY62SF16804A-I

	To Download HY62SF16804A-I Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .